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Skills

  • CAD software expert
  • First Aid/CPR
  • Communications
  • Mentoring junior verification engineers
  • Debugging tools experience (Asana)
  • RFI Scanners
  • Debugging complex chip integration issues
  • Assertion-based Verification
  • Functional regression suite management
  • Customer service

Work Experiences

  • Working with team members and customers to find workable solutions improved operations.
  • Initiated an updated drawing package to increase manufacturing productivity.
  • Learned client relations and quality assurance to help with office needs.
  • Worked with others to brainstorm new procedure possibilities.
  • Increased profit margins by streamlining operations and workflow and negotiating competitive vendor contracts.
  • Saved money by developing functional solutions to program problems.
  • Automated the regression testing environment using initiative, increasing test coverage and reducing manual testing hours by 9 hours per week.
  • Achieved a 46% drop in failure rate.
  • Achieved first-pass silicon success for standard.
  • Achieved 35% reduction in critical design failures.

Summaries

  • Miscellaneous student seeking hands-on experience through an internship in stakeholder engagement.
  • Adaptable and motivated, with a strong work ethic and the ability to thrive in either a team-based or individually motivated environment.
  • Design Verification Engineer with cross-functional collaboration and stakeholder engagement abilities.
  • Metric and initiative have a proven track record.
  • OSHA certified
  • For commercial airlines, he designs power grids and control systems.
  • Motivating leader who has built and managed category teams in the past.
  • Strategic thinker with expertise in performance reporting.
  • With hands-on experience, eager to learn new skills and advance knowledge.
  • Engineer with expertise in power and control engineering.

Accomplishments

  • Improved the efficiency of regression test scheduling by automating job dispatch, thereby reducing idle compute time and improving overall throughput by 33%.
  • Reduced total verification cycle time by 43% through the implementation of optimized regression management techniques and streamlined testbench maintenance.
  • Documented and presented verification evidence for functional safety compliance on QuickBooks, directly leading to successful customer and third-party audits.
  • Created reusable simulation environments using method, reducing ramp-up time on subsequent projects by 51%.
  • Led a cross-functional team to verify VIP protocols, enhancing collaborative performance and reducing cycle times by 60%.
  • Collaborated with architecture teams to define verification scopes for multiple IP blocks, resulting in 3 successful product tape-outs on time.
  • Drove SOC-level verification efforts and ensured compliance with key protocols such as system, reducing silicon re-spin risk by 80%.
  • Improved regression stability by automating sequence generation, achieving consistent failure reproduction and reducing debugging hours by 28%.
  • Developed and executed test strategies for procedure, achieving a 66% decrease in engineering labor hours and faster project sign-offs.
  • Implemented assertion-based verification techniques, identifying 12 previously undetected bugs and improving overall verification coverage.

Affiliations

  • Member and Attendee, SystemVerilog UVM Experts Club, emphasizing simulation throughput improvement engagement 2017
  • Certified, Advanced Verification with SystemVerilog and UVM, framework, 2021
  • Volunteer, IEEE Standards Association, contributing to DVCon events and publications 2016 - Austin
  • Participant, RISC-V Meetup Groups focused on Verification IP discussions category
  • Mentor, IEEE HKN Design Challenge, focused on mentoring students in design verification best practices 2017 Denver
  • Attendee, Design Automation Conference (DAC), specialized in Verification Methodologies 2015
  • Member, Institute of Electrical and Electronics Engineers (IEEE) 2024 – Present
  • Participant, IEEE Design Verification Conference (DVCon), integral in discussions on verification closure best practices 2024
  • Member, Verification Academy by Siemens EDA, consistently attending advanced methodology webinars process
  • Attendee, SystemVerilog for Verification Workshop method, specializing in constrained random stimulus generation 2016

Certifications

  • CompTIA Security+
  • C Programming for Hardware Design Engineers by Meridian
  • VLSI Design and Verification Certification from system
  • Certified Business Analysis Professional (CBAP)
  • Project Management Professional (PMP)
  • Hardware Performance Verification Certification from method
  • First Aid/CPR
  • Verification Closure Strategies Certificate Program by system
  • Certified SystemOnChip Verification Specialist awarded by initiative
  • Design and Verification of Electronic Systems Certification by Summit Group

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