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Skills

  • ASIC design and verification
  • Team building
  • Formal verification techniques
  • Framework equipment
  • MS Office
  • First Aid/CPR
  • Mixed-signal design and verification
  • Team management
  • Regulatory compliance
  • Custom IP architecture

Work Experiences

  • Collaborated with 5 international suppliers on the integration of third-party IP, ensuring seamless functionality post-silicon.
  • Collaborated with front-end and back-end teams.
  • Was in charge of inspecting electrical device manufacturing operations for compliance with safety protocols.
  • Solved program issues, improved operations, and provided excellent customer service.
  • Accelerated go-to-market timelines by 15 months.
  • Achieved 73% error reduction in post-silicon debugging.
  • Aligned IP and chip-level verification efforts.
  • Implemented and approved design control procedures for electrical development in accordance with regulatory guidelines.
  • Collaborated with 10 external teams.
  • Collaborated with international teams across Raleigh to ensure project alignment, significantly enhancing global productivity by 59%.

Summaries

  • Recognized for motivating management team members to achieve their goals and fostering innovative work environments.
  • Strengths in quality assurance and client relations backed up by Miscellaneous training.
  • With a background in power systems, automation, and controls, I'm a focused electrical engineer.
  • With 8 years of experience in telecommunications engineering, I am an electrical engineer.
  • Within Miscellaneous, senior VLSI Design Engineer and outstanding performer in process improvement and cross-functional collaboration.
  • Accelerated go-to-market timelines by 11 months.
  • Architect of cutting-edge low-power SoC designs, achieving a 50% energy efficiency improvement in QuickBooks integration.
  • Collaborative design engineering leader.
  • Achieved 81% energy efficiency improvement.
  • Control and power-delivery systems are well-understood.

Accomplishments

  • Utilized formal verification techniques leading to 8 new functional corner cases detected before tapeout.
  • Performed chip-level Design Rule Check (DRC) and Layout Versus Schematic (LVS) to avoid post-fabrication fixes, saving 5 in rework costs.
  • Implemented automation scripts to smooth workflow during synthesis and place-route steps, saving standard per design cycle.
  • Validated and optimized mixed-signal blocks, directly contributing to a 52% improvement in overall chip yield.
  • Collaborated with process engineers in silicon characterization ensuring voltage, process, and temperature corners met specifications for initiative.
  • Minimized noise effects in mixed-signal simulation environments, resulting in 17 successful silicon tapeouts without revisions.
  • Investigated post-production silicon failures, implementing fixes that increased subsequent yield by 70%.
  • Synthesized FPGA to ASIC conversions in Workday, providing improved timing accuracy and decreased power leaks by 62%.
  • Directed the transition from RTL to gate-level design, ensuring timing closure and reducing design iteration time by 50%.
  • Used Microsoft Excel to develop inventory tracking spreadsheets.

Affiliations

  • IEEE Computer Society Microprocessor Standards Committee, Volunteer
  • Verification Academy – Member, Attended 6 Workshops on FPGA/ASIC Verification
  • Global Semiconductor Alliance (GSA) – Industry Working Groups on Power Reduction
  • Association for Computing Machinery (ACM) – Hardware Verification Community
  • American Society of Safety Professionals
  • National Association of Social Workers
  • IEEE Council on Electronic Design Automation (CEDA), Active Member
  • Institute of Electrical and Electronics Engineers (IEEE) – VLSI Systems and Applications Society
  • Council for Electronic Design Automation (CEDA) – Industry Collaboration Initiatives
  • IEEE International Conference on Communications Circuits and Systems (ICCCAS) – Contributed Paper 2018

Certifications

  • Salesforce
  • Certified VLSI Design Expert (CVDE) from Ironclad Systems
  • Certified Chip Layout Designer by Northwind – Experience with Microsoft Excel
  • RTL Design and Verification Certification from Vantage
  • Certified ASIC Synthesis Engineer by Lakeside Partners
  • CompTIA Network+
  • Mentor Graphics Certified Verification Engineer (CVE)
  • CompTIA Security+
  • Certified Power-Aware Digital Design Engineer from system
  • Certified ASIC Design and Verification Professional by Vantage

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