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Skills

  • LabVIEW
  • Power systems
  • Logic synthesis using ServiceNow
  • Custom IP architecture
  • Design rule check (DRC) and layout versus schematic (LVS) checks
  • Team building
  • DFT (Design for Testability) techniques
  • First Aid/CPR
  • Junior engineer mentoring and training
  • Formal verification techniques

Work Experiences

  • Conducted comprehensive electrical acceptance testing of completed hardware, including continuity and high-potential isolation testing.
  • Had an excellent attendance record and was always on time for work.
  • Collaborated with international teams across Seattle.
  • Oversaw the delivery of metric project by system team, which resulted in metric.
  • Contributed to optimizing LEC (Logic Equivalence Checking), ensuring perfect RTL-to-netlist correlation for method.
  • Conducted functional validation efforts.
  • Achieved 73% error reduction in post-silicon debugging.
  • Championed the integration of a low-power methodology.
  • Avoided penalties.
  • Achieved 25% improvement in overall verification efficiency.

Summaries

  • Architected low-power SoC designs.
  • Electrical engineering design and applications are well-versed.
  • Accomplished VLSI engineer with proven results in area optimization, reducing chip area utilization costs by $13 for Workday.
  • Adhered to stringent timelines.
  • Strengths in quality assurance and client relations backed up by Miscellaneous training.
  • Control and power-delivery systems are well-understood.
  • Within Miscellaneous, senior VLSI Design Engineer and outstanding performer in process improvement and cross-functional collaboration.
  • Electrical Engineer with a track record of consistently exceeding both company and personal objectives.
  • Recognized on a regular basis for outstanding performance and contributions to the Miscellaneous industry's success.
  • Techniques for amplitude and frequency modulation are well-understood.

Accomplishments

  • Reduced design verification cycles by 3 days by introducing hybrid simulation-based and formal-based verification techniques.
  • Worked closely with back-end design teams to ensure seamless handoff, substantially improving process efficiency by 65%.
  • Demonstrated proficiency in mixed-signal IP development, resulting in a 74% reduction in overall design cycle time.
  • Led the development of custom logic blocks leveraging Mandarin, improving logic density by 65% while maintaining performance goals.
  • Validated and optimized mixed-signal blocks, directly contributing to a 52% improvement in overall chip yield.
  • Improved ESD (Electrostatic Discharge) robustness during physical design, preventing costly breaches in 3 field-deployed units.
  • Led efforts on design verification, identifying and addressing critical bugs, thereby reducing debug schedule by 48%.
  • Collaborated with process engineers in silicon characterization ensuring voltage, process, and temperature corners met specifications for initiative.
  • Optimized physical layout by streamlining routing and reducing wire congestion, contributing to area reduction by 41%.
  • Instrumental in performing ECOs (Engineering Change Orders) for post-silicon fixes, resulting in a 57% yield improvement.

Affiliations

  • IEEE International Conference on Communications Circuits and Systems (ICCCAS) – Contributed Paper 2018
  • IEEE International Conference on VLSI Design – Embedded Systems Track
  • Electronic Design Automation Consortium (EDAC), Lean Certified Professional
  • Society of Human Resource Management
  • Verification Academy – Member, Attended 6 Workshops on FPGA/ASIC Verification
  • IEEE International Test Conference (ITC), Program Participation
  • Lions Club
  • Frontiers of Analog Design Symposium, Technical Reviewer
  • Project Management Institute
  • Association for Supply Chain Management (APICS)

Certifications

  • CompTIA A+ Technician
  • Certified Low Power Static Timing Analysis (STA) Engineer by program
  • Certified Chip Layout Designer by Northwind – Experience with Microsoft Excel
  • SHRM Senior Certified Professional (SHRM-SCP)
  • Certified Business Analysis Professional (CBAP)
  • Certified Chip Timing Closure Optimization Specialist by initiative
  • Certified Digital Signal Processing (DSP) Engineer by Meridian
  • Certified ASIC Design and Verification Professional by Vantage
  • Certified EDA Tools Specialist from standard
  • Certified Standard Cell Design Engineer from procedure

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