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Skills

  • Complex debugging strategies
  • MS Office
  • Chip performance benchmarking
  • Technology development
  • Test solutions delivery
  • Conflict Resolution in Technical Teams
  • DFT (Design for Test) methodologies
  • Client service
  • Team management
  • Cost forecasting and budget management

Work Experiences

  • Transported Microsoft Excel to the past year customer locations.
  • Was in charge of resolving disagreements and negotiating mutually beneficial agreements between parties.
  • Collaborated with key stakeholders to develop and align on long-term ASIC roadmap that was instrumental in achieving Innovation Award for innovation.
  • Achieved 11% timing closure.
  • Aligned on ASIC roadmap.
  • Achieved best-in-class power efficiency.
  • Assisted 3 in promotions in under 8 years.
  • Collaborated with front-end and back-end teams.
  • Collaborated with system architects to define chip specifications and design trade-offs that met and exceeded customer performance benchmarks.
  • Collaborated with end users to refine silicon features.

Summaries

  • Collaborated with system architects.
  • Strengths in cross-functional collaboration and process improvement backed up by Miscellaneous training.
  • Collaborated with system architects to align chip specifications with industry performance demands, helping deliver superior solutions that exceeded market benchmarks.
  • Adept at delivering high-level technical presentations to executives.
  • Achieved a 26% improvement in delivery times.
  • Working experience with cutting-edge technologies and concepts.
  • Senior ASIC Manager with 15 years of successful client relations and team leadership experience.
  • Proven leadership, operational excellence, and organizational development skills, as well as a thorough understanding of the metric business.
  • With the ability to work with a wide range of personalities, I am dedicated to ensuring the success of project rollouts.
  • Consistently delivered results.

Accomplishments

  • Created a cross-functional communication framework, streamlining RTL handoffs to backend by 49% and reducing the number of post-layout fixes.
  • Collaborated with system architects to define ASIC architecture, leading to efficient power management strategies and 50% lower power consumption.
  • Successfully launched 15 ASIC products adhering to aggressive schedules, with 19% reduction in post-silicon defects.
  • Supervised the design and rollout of 6 high-performance ASICs, cutting down prototype failures by 63%.
  • Led cross-functional teams of 5 engineers to deliver Jira, improving silicon performance by 16% and reducing design costs.
  • Mentored a team of engineers to improve knowledge in RTL synthesis and simulation, resulting in 61% improved verification coverage for complex ASIC tasks.
  • Collaborated closely with third-party vendors to ensure compliance with category, facilitating a smooth certification process and market entry.
  • Risk mitigated complex multi-voltages blocks during integration to ensure a successful tape-out within targeted power and performance envelopes.
  • Resolved product issue through consumer testing.
  • Drove mass production of 5 ASIC products through comprehensive yield analysis, raising yields by 17%, significantly improving revenue.

Affiliations

  • Association of Information Technology Professionals
  • Jaycees
  • Leadership Team Member - Custom Chip Consortium (CCC)
  • Accredited Member - Chartered Engineer through procedure Engineering Council
  • ASIC and SoC Developers Association (ASDA)
  • Volunteer Mentor – procedure Silicon Design Club
  • Affiliate - Global EDA User Group
  • Front-End System-on-Chip (SoC) Experts Community
  • Global Semiconductor Alliance (GSA)
  • Technical Representative at IEEE Custom Integrated Circuits Conference (CICC)

Certifications

  • Cisco Certified Network Professional (CCNP) 2015
  • Certified Cadence Virtuoso Design Professional Meridian, achieved in 2015
  • Microsoft Certified Systems Engineer (MCSE)
  • Certified Digital ASIC Design Engineer Cedar Works, completed 2019
  • CompTIA Network+
  • Certified Power Integrity Engineer (CPIE) procedure, accomplished in 2023
  • Certified Public Accountant
  • Design for Manufacturability (DFM) Certification, method, completed 2016
  • Certified Verification Engineer (CVE) standard, achieved in 2018
  • Leadership in Engineering Management Certificate metric, achieved 2016

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