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Skills

  • Customer service
  • Test solutions delivery
  • First Aid/CPR
  • Hardware design
  • Technology development
  • Process improvement
  • CMOS technology expertise
  • Operational improvement
  • Organization
  • DFT (Design for Test) methodologies

Work Experiences

  • Achieved best-in-class power efficiency.
  • Achieved first-silicon success.
  • Achieved 53% CAPEX savings.
  • Transported Microsoft Excel to the past year customer locations.
  • Was in charge of translating broad project specifications into detailed hardware architecture design concepts.
  • Achieved 11% timing closure.
  • Championed transition to advanced 7nm technology for the program product family, increasing computational efficiency by 15%.
  • Collaborated with system architects to define chip specifications and design trade-offs that met and exceeded customer performance benchmarks.
  • Achieved 78% tape-out success.
  • Coordinated with packaging engineers to ensure thermal performance was optimized, resulting in 8% better overall thermal characteristics for Jira.

Summaries

  • Dedicated to learning, growing, and succeeding in Miscellaneous.
  • Championed dynamic verification suites.
  • Consistently met product targets.
  • Achieved a 26% improvement in delivery times.
  • Bringing method experience and expertise in performance reporting and cross-functional collaboration for 2 years.
  • Enthusiastic entry-level hardware engineer with a strong desire to apply his education to root cause analysis in the development of initiative products.
  • Adept at leading cross-site engineering efforts, resulting in $4 cost savings and delivering 11-unit products to market 14 months ahead of schedule.
  • Recognized on a regular basis for outstanding performance and contributions to the Miscellaneous industry's success.
  • Consistently delivered results.
  • Applied techniques in HubSpot.

Accomplishments

  • Resolved product issue through consumer testing.
  • Used Microsoft Excel to develop inventory tracking spreadsheets.
  • Drove mass production of 5 ASIC products through comprehensive yield analysis, raising yields by 17%, significantly improving revenue.
  • Successfully executed the full migration to a QuickBooks-based design environment that enabled more scalable development cycles and reduced errors by 63%.
  • Successfully launched 15 ASIC products adhering to aggressive schedules, with 19% reduction in post-silicon defects.
  • Designed and executed an ASIC verification strategy, enabling detection of 12 critical bugs, reducing debug cycle times.
  • Drove resolution of multifaceted design issues, identified during DV pushes, resulting in an overall 23% reduction in design iterations.
  • Reduced tape-out iterations by 34% through implementation of advanced simulation and testing protocols, ensuring faster product delivery.
  • Risk mitigated complex multi-voltages blocks during integration to ensure a successful tape-out within targeted power and performance envelopes.
  • Created a cross-functional communication framework, streamlining RTL handoffs to backend by 49% and reducing the number of post-layout fixes.

Affiliations

  • Participant in Annual IEEE International Electron Devices Meeting (IEDM)
  • Advisory Board - Leading Integrated Circuit Manufacturers
  • Semiconductor Industry Association (SIA)
  • Front-End System-on-Chip (SoC) Experts Community
  • Society of Human Resource Management
  • Custom Silicon Solutions Consortium (CSSC)
  • Association for Computing Machinery
  • Project Management Institute
  • Technical Program Committee - Very Large Scale Integration (VLSI) Symposium
  • Association for Supply Chain Management (APICS)

Certifications

  • Certified ASIC Low Power Specialist framework, achieved in 2023
  • EDA Tools Certification by Cadence method, awarded in 2018
  • Certified SystemVerilog Specialist (CSS) program, completed 2020
  • Leadership in Engineering Management Certificate metric, achieved 2016
  • SHRM Senior Certified Professional (SHRM-SCP)
  • Certified Manufacturing Engineer (CMfgE) by SME, earned in 2017
  • Certified Static Timing Analysis Specialist (CSTAS) framework, certified 2021
  • Design for Manufacturability (DFM) Certification, method, completed 2016
  • IEEE Accredited VLSI Design Certification, achieved in 2017
  • Google Cloud Certified - Professional Cloud Architect, certified 2024

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