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Skills

  • Procedure equipment
  • Process improvement
  • Implementation planning
  • Design automation tools development
  • Problem resolution
  • Multi-vendor IP block management
  • Integration of third-party IP
  • Relationship development
  • Customer service
  • MS Office

Work Experiences

  • Achieved 35% timing closure success rate.
  • Had an excellent attendance record and was always on time for work.
  • Aligned with customer requirements.
  • Addressed issues across 16 high-frequency domains.
  • Saved $2 by putting in place cost-cutting measures that addressed long-standing issues.
  • Caught 2 design issues pre-silicon.
  • Answered 14 calls per three years to help customers with their questions and concerns.
  • Achieved flawless support for 4 high-speed standards.
  • Achieved a 5% throughput increase for Asana.
  • Achieved a 51% reduction in manual errors.

Summaries

  • Clear understanding of client relations and strategic planning as well as data analysis training.
  • Accelerated product schedules by 9 months.
  • Accomplished Senior ASIC Design Engineer with expertise in low-power architecture design, delivering 75% improvements in power efficiency for next-generation Tableau. Solid experience with FPGA prototyping and verification for high-performance applications.
  • Using a variety of technology resources, achieves intended concepts in accordance with project requirements.
  • Dedicated to learning, growing, and succeeding in Miscellaneous.
  • Adept at bridging the gap between architectural requirements and design execution, contributing to a 82% improvement in overall power efficiency while enhancing team productivity.
  • Achieved substantial cost savings.
  • Achieved 67% first-pass silicon yield for Power BI.
  • Costs were consistently reduced while profits were increased.
  • Achieved cost savings of $13.

Accomplishments

  • Defined and executed synthesis and STA constraints, achieving 38% timing closure success for chips operating at 4 GHz, surpassing company performance benchmarks.
  • Conducted static timing analysis across multiple process corners to ensure timing closure, achieving a 59% increase in design reliability across all configurations.
  • Implemented advanced RTL optimizations, enhancing chip performance by 72% while lowering area utilization by 27%, directly reducing overall manufacturing costs by $8.
  • Optimized clock tree synthesis for a standard chip, increasing critical path performance by 21% and reducing power usage by 46%, resulting in a more energy-efficient design.
  • Spearheaded cross-functional collaboration with RTL, synthesis and verification teams, minimizing design cycle time by 30%.
  • Introduced power gating techniques in the design to minimize standby power consumption, leading to a 77% reduction in total system power.
  • Restructured the verification flow using Salesforce, improving test coverage by 60% and reducing bug escape rates in the design process.
  • Led design for testability (DFT) strategy for program, incorporating boundary-scan and built-in-self-test (BIST), reducing manufacturing test time by 62%.
  • Developed and tested a low-power Adobe Creative Suite design that reduced leakage current by 43%, improving power efficiency and extending battery life in mobile applications.
  • Refined chip power distribution network, reducing IR drop by 42% and enabling higher performance at maximum frequency.

Affiliations

  • Conference Speaker at Global Semiconductor Alliance (GSA)
  • Association of Information Technology Professionals
  • Association for Computing Machinery
  • IEEE International Solid-State Circuits Conference (ISSCC) Participant
  • American Marketing Association
  • Jaycees
  • IEEE Electron Devices Society (EDS)
  • National Society of Professional Engineers (NSPE)
  • VLSI Design and CAD Society
  • Board Member of the International Electronics Manufacturing Initiative (iNEMI)

Certifications

  • Microsoft Certified Systems Engineer (MCSE)
  • Synthesis Design Certification by Synopsys Design Compiler
  • Salesforce
  • Apple Certified Associate (ACA)
  • Certified Public Accountant (CPA)
  • Physical Design Verification (PDV) Professional Certification, Lakeside Partners
  • Certified ASIC Design Specialist (CADS)
  • Cisco Certified Network Associate (CCNA)
  • CompTIA Network+
  • Certified Public Accountant

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