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Skills

  • Team management
  • Chip architecture redesign
  • Client service
  • Digital signal processing (DSP) algorithm implementation
  • Hardware design
  • Hardware tools
  • Failure analysis and resolution
  • Procedure equipment
  • Ethernet switching
  • Budgets

Work Experiences

  • Achieved a data rate of 10 Gbps.
  • Achieved a 66% reduction in critical path delay.
  • Had an excellent attendance record and was always on time for work.
  • Achieved a 17% increase in first-pass silicon success.
  • Completed 6 projects.
  • Worked with network engineering staff to assess hardware and software requirements for the development of a new system.
  • Analyzed timing reports.
  • Collaborated with back-end engineers.
  • Conducted multi-corner static timing analysis.
  • Analyzed timing reports and engineered solutions that brought Workday design from failing timing closure to passing all sign-off criteria in under two years.

Summaries

  • ASIC Design Engineer passionate about merging complex designs with real-world manufacturability. Delivered a Asana ASIC chip early while successfully achieving a 77% reduction in timing bottlenecks.
  • Boosted performance on high-density chips.
  • Overall morale and productivity are boosted by experience in policy development and staff management procedures.
  • Achieved data rates of 10 Gbps.
  • ASIC Design Engineer is a multi-talented ASIC Design Engineer who is consistently rewarded for planning and operational improvements.
  • Bringing program experience and expertise in vendor management and team leadership for 14 years.
  • Avid techno-enthusiast.
  • Achieved reductions through advanced optimizations.
  • Experienced hardware engineer with a track record of managing hardware development and support projects.
  • Achieved project savings of $166,000.

Accomplishments

  • Collaborated closely with back-end design teams to resolve timing closures, bringing project back on track within two years.
  • Played key role in implementing formal verification techniques, reducing bug occurrence by 65% before sign-off.
  • Introduced formal CDC checks for multi-clock domain designs, decreasing silicon failure probability by 80%.
  • Collaborated with DFT teams to integrate scan chains, improving test coverage to 69% and expediting the validation process.
  • Successfully achieved first-pass silicon success across Workday, saving estimated 16 months of re-spinning.
  • Orchestrated cross-functional team efforts to optimize clock-tree synthesis, resulting in 29% reduction in clock skew.
  • Used Microsoft Excel to develop inventory tracking spreadsheets.
  • Chaired cross-disciplinary task force to define and implement CDC guidelines, resulting in a measurable reduction in metastability incidents.
  • Created extensive design guides for the team, reducing onboarding time for new ASIC engineers by two years.
  • Developed custom verification models for Adobe Creative Suite, decreasing bug detection time by 72% during simulation phases.

Affiliations

  • Attained Certification for standard Automation Workflow Design
  • National Association of Social Workers
  • Association for Computing Machinery
  • IEEE Custom Integrated Circuits Conference (CICC) Presenter
  • Freemason
  • IEEE Standards Association
  • Fostered Mentorship Program with initiative ASIC Design Course
  • Certified ASIC Design Tool Instructor for Ironclad Systems
  • IEEE Solid-State Circuits Society (SSCS)
  • Design Automation Conference (DAC) participation

Certifications

  • High-Speed FPGA and ASIC Design Certification by initiative (2019)
  • Google Certified Professional Cloud Architect
  • IEEE Certified VHDL Expert (2017)
  • Certified Project Management for EDA Professionals (CPME) (2023)
  • Synopsys PrimeTime Certification (2021)
  • ASIC Design for Security and Cryptography Certification (2021)
  • Cisco Certified Network Associate (CCNA)
  • Certified SystemVerilog Design Engineer (Verilog HDL-Specialized) (2020)
  • SHRM Senior Certified Professional (SHRM-SCP)
  • Physical Design for ASIC Certification (Cadence/ Synopsys Suite) (2020)

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