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Skills

  • Cross-functional team collaboration
  • Business operations
  • Circuit-Level Debugging
  • Adobe Creative Suite expertise
  • Project leadership
  • Post-Silicon Validation
  • Low Power Design Verification
  • Advanced Coverage-Driven Verification
  • Mentoring and Training Engineers
  • First Aid/CPR

Work Experiences

  • Aligned plans with customer requirements.
  • Championed the adoption of formal verification techniques.
  • Boosted overall team coverage from 60% to 23%.
  • Adopted across 12 sites globally.
  • Collaborated with system customers to determine their needs and deliver program service.
  • Had an excellent attendance record and was always on time for work.
  • Conducted thorough verification.
  • Defined verification plans for Workday that aligned with customer requirements, contributing to Employee of the Year for technical excellence.
  • Collaborated with tool vendors.
  • Automated the regression testing environment using Python.

Summaries

  • Achieved 55% defect reduction over 2017.
  • Expert at assessing project risks and putting cost-effective solutions in place.
  • Accomplished professional in verification strategy planning.
  • Championed formal property verification frameworks.
  • Collaborative Verification Engineer specialized in RTL verification with rich experience in designing complex test cases that improved first-pass success rates by 6%.
  • Architected simulation environments.
  • Adaptable and results-driven, I led the integration of new tools and methods that increased coverage by 56% and reduced test phase defects across 18 projects.
  • Achieved zero late-stage re-spins.
  • Adept at using assertion-based verification to identify 18 critical protocol violations before tapeout, leading to significant cost savings and achieving early certification approval.
  • Aided in the early release of SAP.

Accomplishments

  • Co-developed scalable testbenches in SystemVerilog for an IP block, improving verification coverage efficiency by 72% across multiple projects.
  • Authored comprehensive best practice documentation for UVM-based constrained random verification adopted by 17 worldwide design centers.
  • Led the development of a verification plan for initiative, resulting in reduced post-silicon design fixes and improved time-to-market.
  • Optimized random testbench generation, improving verification efficiency by 15% across FPGA and ASIC flows.
  • Spearheaded system-level verification effort for a QuickBooks project, contributing to 18 tape-outs with no last-minute RTL changes.
  • Improved FPGA debug feedback signal visibility using waveform analysis, reducing the root-cause identification time by 54%.
  • Reduced non-deterministic failures in nightly regression runs by 16% through continuous tuning of the verification test environment.
  • Introduced and maintained a metrics-driven approach for tracking verification closure, achieving verification milestones 7 weeks ahead of the original deadline.
  • Evaluated and integrated new verification tools/flows, improving testbench execution speed by 67% during high-traffic regression cycles.
  • Documented and resolved method which led to initiative.

Affiliations

  • Lead Mentor for Engineering Student Group focused on Verification at category
  • GlobalFoundries Partner Ecosystem
  • Electronic Design Automation Consortium
  • Chair of Hardware Verification Special Interest Group
  • Society of Women Engineers
  • International Council of Nurses
  • Association of Information Technology Professionals
  • Silicon Integration Initiative (Si2)
  • Participated in the Advanced Regression Tools Seminar 2023
  • Global Semiconductor Alliance (GSA)

Certifications

  • Post-Silicon Validation Expert Certification – Lakeside Partners
  • SystemVerilog Assertions (SVA) Certifications - Vantage
  • Project Management Professional (PMP)
  • Low Power Design Verification Specialist – Adobe Creative Suite
  • Cisco Certified Internetwork Expert (CCIE)
  • Salesforce
  • Certified Public Accountant (CPA)
  • Certified ASIC Verification Professional – Brightline
  • IEEE Certified Professional Software Developer in Verification and Validation
  • Verification IP Specialist (VIP)- Jira

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