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Skills

  • CCTV
  • Organization
  • Supervision
  • Advanced timing sign-off for sub-nm technology nodes
  • Insurance billing
  • Handling design for manufacturability (DFM)
  • Communications
  • Complex routing of multi-million gate designs
  • Team management
  • Hardware and firmware design

Work Experiences

  • Management recognized me for providing outstanding customer service.
  • Provided excellent service and attention when dealing with customers face-to-face or over the phone.
  • Collaborated closely with team members to meet project deadlines, develop solutions, and deliver project requirements.
  • Achieved significant improvements in accuracy.
  • Achieved significant improvements in runtime.
  • Achieved project goals in 2015.
  • Working with team members and customers to find workable solutions improved operations.
  • Electrical equipment, facilities, and systems were designed and implemented by me.
  • Finished program of project, which resulted in system.
  • Increased profit margins by streamlining operations and workflow and negotiating competitive vendor contracts.

Summaries

  • Achieved 21% success in reducing critical path block delays.
  • Results-oriented Electrical Engineer committed to developing cutting edge electronic equipment. Experience working with top electronic manufacturers, including method companies.
  • Physical Design Engineer with project management and stakeholder engagement abilities.
  • Working experience with leading electronic manufacturers, including category firms.
  • Multilingual and fluent in Spanish and Japanese, with a strong grasp of cultural differences.
  • Achieved noise reduction.
  • Communicative and team-oriented, with Asana expertise.
  • With hands-on experience, eager to learn new skills and advance knowledge.
  • Electrical Engineer with a passion for developing cutting-edge electronic equipment.
  • Achieved 68% improvement in signal integrity.

Accomplishments

  • Spearheaded the development of power and area estimation models for 17 complex blocks, achieving an area savings of 16% on system-nm designs.
  • Worked directly with back-end and RTL engineers to define physical design guidelines, leading to first-pass success for initiative-nm process technology in 2017.
  • Implemented leakage reduction strategies that helped cut power consumption by 16%, extending battery life in portable devices for metric.
  • Proactively debugged LVS/DRC violations in multi-layer metal stacks, allowing for clean layouts and first-time silicon success in metric-nm designs.
  • Developed robust CTS strategies that enabled clock distribution networks with 19% higher efficiency, ensuring all timing requirements were met under tight production schedules.
  • Reduced metal congestion and achieved optimal routing for 7 complex SoC designs, meeting area and timing constraints under aggressive schedules.
  • Led routing optimization strategies for 3 layers in a complex floorplan, ensuring that timing, IR drop, and electromigration rules were all met before tape-out.
  • Developed and executed physical verification (DRC and LVS) flows that identified 15 errors early in the design stage, preventing costly respins later.
  • Led a cross-functional team in a high-stakes project, integrating various blocks and ensuring power, performance, and area (PPA) goals were met within a 40% margin of variation.
  • Automated the sign-off closure process for 18 SoC tape-outs by developing custom verification flows, reducing the timeline to silicon by 23%.

Affiliations

  • Presenter, International Conference on VLSI and CAD (VLSICAD) 2019
  • Advisory Board Member, Research Society of Electrical Engineering framework
  • Workshop Leader, Electromigration Challenges in processnm Conference 2016
  • Certificant, Synopsys Certified Specialist - Digital Implementation Tools 2019
  • Board Member, Physical Design Chapter, standard Alumni Association category
  • Certificant, Advanced Floorplanning Techniques Workshop, 2015 Cedar Works
  • Certificant, Mentor Graphics Certified Physical Design Expert 2017
  • Presenter, International Symposium on Low Power Electronics and Design (ISLPED) 2022
  • Member, IEEE Computer Society Special Interest Group on VLSI Design
  • Advisory Role, Global Semiconductor Alliance (GSA) Technical Working Group

Certifications

  • Multi-Mode Multi-Corner Signoff (MMMC) Verification Certification - Salesforce
  • Certified Public Accountant (CPA)
  • Project Management Professional (PMP)
  • American Academy of Financial Management (AAFM)
  • Certified Low Power Design Expert (LPDFEX) - Asana
  • Certified Design for Manufacturing Professional (DFM) - Cedar Works
  • Design for Manufacturability Methods Certification - Vantage
  • Certified Expert in OCV and PVT Analysis - initiative
  • CompTIA A+ Technician
  • Certified Timing Verification Engineer with PrimeTime - Ironclad Systems

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