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Skills

  • Signal generators
  • DRC and LVS verification and debugging
  • Complex routing of multi-million gate designs
  • First-pass silicon success rates
  • Inventory management
  • Operational improvement
  • Handling design for manufacturability (DFM)
  • Communications
  • Hardware and firmware design
  • Clock gating techniques for power reduction

Work Experiences

  • Answered 10 phone calls per 18 months to assist customers.
  • Saved money by developing functional solutions to process problems.
  • Achieved results in 2017.
  • Finished program of project, which resulted in system.
  • Assisted, advised, and mentored employees at all levels.
  • Achieved President's Club for design excellence by eliminating framework errors from full-custom designs, reducing post-layout fixes.
  • Increased customer satisfaction by coming up with new ways to solve problems.
  • Achieved project goals in 2015.
  • Achieved tape-out for Jira.
  • Achieved clock skew reductions.

Summaries

  • Results-oriented Miscellaneous professional with cross-functional collaboration, stakeholder engagement, and risk assessment strengths.
  • Results-oriented Electrical Engineer committed to developing cutting edge electronic equipment. Experience working with top electronic manufacturers, including method companies.
  • Miscellaneous student seeking hands-on experience through an internship in process improvement.
  • Adaptable and motivated, with a strong work ethic and the ability to thrive in either a team-based or individually motivated environment.
  • Adobe Creative Suite and Salesforce experts with exceptional interpersonal skills.
  • PMP certified
  • Working with stakeholders and corporate teams is a breeze for this strong relationship builder.
  • Achieved a 50% improvement in timing closure.
  • Achieved 21% success in reducing critical path block delays.
  • Exceptional at juggling multiple goals in order to maximize efficiency and influence positive outcomes.

Accomplishments

  • Implemented leakage reduction strategies that helped cut power consumption by 16%, extending battery life in portable devices for metric.
  • Developed robust CTS strategies that enabled clock distribution networks with 19% higher efficiency, ensuring all timing requirements were met under tight production schedules.
  • Reduced total power consumption of core logic blocks by 36% through implementation of clock gating and optimization of the power grid, leading to improved efficiency.
  • Collaborated with IP and package teams to address cross-domain integration challenges, achieving ITIL standards for Microsoft Excel.
  • Successfully delivered multiple high-frequency designs with zero electromigration and IR drop violations on standard-nm nodes, enhancing long-term chip reliability for clients.
  • Achieved successful tape-out of 11 multi-million gate designs, managing end-to-end ownership from synthesis through final GDS deliverables for framework.
  • Proactively debugged LVS/DRC violations in multi-layer metal stacks, allowing for clean layouts and first-time silicon success in metric-nm designs.
  • Worked extensively with process and initiative for final timing closure and sign-off, preventing costly delays and ensuring on-time product launch.
  • Implemented robust clock mesh network schemes that led to the reduction of uncertainties by 42%, resulting in outstanding timing closure for high-speed projects.
  • Achieved first-pass silicon success for program-nm technology, leading to a reduction in design revision cycles and saving the company $18 in project costs.

Affiliations

  • Member, IEEE Computer Society Special Interest Group on VLSI Design
  • Participant, International Conference on Physical Design (ICPD) 2019
  • Presenter, International Conference on VLSI and CAD (VLSICAD) 2019
  • Certificant, Advanced Floorplanning Techniques Workshop, 2015 Cedar Works
  • Graduate Member, IEEE Electron Devices Society (EDS)
  • Participant, RTL Synthesis Tools Bootcamp - Microsoft Excel, 2023
  • Participant, IEEE International Symposium on Circuits and Systems (ISCAS) 2017
  • Contributor, International Society for Co-Design of Hybrid Systems (CoHS)
  • Chapter Leader, Toastmasters for Engineers, Raleigh 2016
  • Attendee, DAC Design Automation Conference 2016

Certifications

  • ServSafe
  • IR Drop Analysis Certification - system
  • Apple Certified Associate (ACA)
  • Cisco Certified Network Associate (CCNA)
  • Certified Power Integrity Professional - Northwind
  • Association for Project Management (APM)
  • Microsoft Office Specialist (MOS)
  • Salesforce
  • Certified Integration and Physical Verification Professional - Summit Group
  • Advanced IC Design and Layout Course Completion - Summit Group

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