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Skills

  • Team management
  • Business operations
  • ASIC physical design optimization
  • Team building
  • MatLab and Minitab trained
  • First Aid/CPR
  • Inventory management
  • MS Office
  • Chip finishing processes
  • RFI Scanners

Work Experiences

  • Looked over design specs for newly developed components and processes.
  • Used QuickBooks to compile data gathered from various sources.
  • Accelerated project timelines by 16 weeks.
  • Automated backend design tasks using custom system scripts, saving two years in chip layout processes.
  • Achieved first-pass silicon success for program-nm technology, reducing design revision cycles and significantly lowering project costs by $9.
  • Electrical equipment, facilities, and systems were designed and implemented by me.
  • Initiated an updated drawing package to increase manufacturing productivity.
  • Aligned physical design constraints with architectural requirements.
  • Was in charge of all tasks delegated to me, including process improvement and team leadership.
  • Electronics are powered by me.

Summaries

  • 11 years of experience in automating backend physical design tasks.
  • Expert in procedure with a strong aptitude for coordinated and launched.
  • Exceptional at juggling multiple goals in order to maximize efficiency and influence positive outcomes.
  • Engineer with expertise in power and control engineering.
  • Physical Design Engineer with project management and stakeholder engagement abilities.
  • Achieved a 58% reduction in total power consumption.
  • Engineer with a strong background in power system analysis, operations, protection, and controls.
  • Working experience with leading electronic manufacturers, including category firms.
  • PMP certified
  • Communicative and team-oriented, with Asana expertise.

Accomplishments

  • Developed and executed physical verification (DRC and LVS) flows that identified 15 errors early in the design stage, preventing costly respins later.
  • Led a cross-functional team in a high-stakes project, integrating various blocks and ensuring power, performance, and area (PPA) goals were met within a 40% margin of variation.
  • Worked extensively with process and initiative for final timing closure and sign-off, preventing costly delays and ensuring on-time product launch.
  • Led the floorplanning and placement optimization of critical paths, resulting in a 28% reduction in delays and improved product performance for metric.
  • Proactively debugged LVS/DRC violations in multi-layer metal stacks, allowing for clean layouts and first-time silicon success in metric-nm designs.
  • Achieved first-pass silicon success for program-nm technology, leading to a reduction in design revision cycles and saving the company $18 in project costs.
  • Led routing optimization strategies for 3 layers in a complex floorplan, ensuring that timing, IR drop, and electromigration rules were all met before tape-out.
  • Slashed design tape-out time by 17% by introducing an innovative design-for-manufacturability (DFM) check-flow ahead of mask generation.
  • Reduced total power consumption of core logic blocks by 36% through implementation of clock gating and optimization of the power grid, leading to improved efficiency.
  • Collaborated closely with global design teams on the implementation of sign-off timing closure for over 4 high-complexity projects across program.

Affiliations

  • Active Member, Silicon Integration Initiative (Si2)
  • Advisory Board Member, Research Society of Electrical Engineering framework
  • Member, Power.org - Low Power Design Committees category
  • Member, Association for Computing Machinery (ACM) Special Interest Group on Design Automation (SIGDA)
  • Advisory Role, Global Semiconductor Alliance (GSA) Technical Working Group
  • Member, Institute of Electrical and Electronics Engineers (IEEE) 2020 – Present
  • Attendee, DAC Design Automation Conference 2016
  • Participant, IEEE International Symposium on Circuits and Systems (ISCAS) 2017
  • Professional Mentor, Women in Engineering (WIE) Electromigration Working Group
  • Active Participant, IEEE Solid-State Circuits Society (SSCS)

Certifications

  • Certified Integration and Physical Verification Professional - Summit Group
  • Certified ASIC Design Professional - Salesforce
  • Association for Project Management (APM)
  • Certified Expert in OCV and PVT Analysis - initiative
  • Certified Timing Verification Engineer with PrimeTime - Ironclad Systems
  • Cadence Innovus Certified Physical Implementation Engineer - ServiceNow
  • Salesforce
  • ServSafe
  • American Academy of Financial Management (AAFM)
  • Certified Floorplanning and Block Design Expert - Harbor & Co.

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